Document Type

Article

Publication Date

1-28-2026

Publication Title

IEEE Access

Volume

14

First page number:

18455

Last page number:

18475

Abstract

RISC-V is a free and open-standard ISA based on RISC principles, allowing anyone to design, manufacture, and sell RISC-V chips and software. Its flexibility and growing ecosystem have made it popular in research, education, and industry, increasing the need for educational materials. This paper provides an in-depth description of the RVfpga course, which offers a solid introduction to computer architecture using the RISC-V instruction set and FPGA technology. It focuses on providing hands-on experience with real-world RISC-V cores, the VeeR EH1 and EL2 cores, developed by Western Digital and hosted by ChipsAlliance. The course targets students and educators in computing-related fields, enabling them to integrate practical RISC-V knowledge into their curricula. The course materials, which include detailed labs, setup guides, and the full SoC source code in System Verilog, are available for free. Students learn to compile, debug, and run C and assembly programs, to interact with built-in peripherals, to extend the SoC, and to explore microarchitectural features.

Keywords

Computer architecture; computer science education; education courses; microarchitecture

Disciplines

Computer and Systems Architecture | Systems and Communications

File Format

PDF

File Size

2700 KB

Language

English

Rights

IN COPYRIGHT. For more information about this rights statement, please visit http://rightsstatements.org/vocab/InC/1.0/

Creative Commons License

Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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